Verilog

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Verilog-95

Verilog 2001

Verilog 2005

SystemVerilog

Örnek

module main;
initial 
 begin
  $display("Merhaba dunya!");
  $finish;
 end
endmodule

module toplevel(clock,reset);
input clock;
input reset;



reg flop1;
reg flop2;



always @ (posedge reset or posedge clock)
if (reset)
 begin
  flop1 <= 0;
  flop2 <= 1;
 end
else
 begin
  flop1 <= flop2;
  flop2 <= flop1;
 end
endmodule

module Div20x (rst, clk, cet, cep, count,tc);
// TITLE `Divide-by-20 Counter with enables`
// enable CEP is a clock enable only
// enable CET is a clock enable and
// enables the TC output
// a counter using the Verilog language



parameter size = 5;
parameter length = 20;



input rst; // These inputs/outputs represent 
input clk; // connections to the module.
input cet;
input cep;



output [1] count;
output tc;



reg [2] count; // Signals assigned 
          // within an always 
          // (or initial)block 
          // must be of type reg



wire tc; // Other signals are of type wire



// The always statement below is a parallel
// execution statement that
// executes any time the signals 
// rst or clk transition from low to high



always @ (posedge clk or posedge rst)
if (rst) // This causes reset of the cntr
 count <= 5`b0;
else
if (cet && cep) // Enables both true
 begin
  if (count == length-1)
   count <= 5`b0;
  else
   count <= count + 5`b1; // 5`b1 is 5 bits 
 end            // wide and equal 
               // to the value 1.



// the value of tc is continuously assigned 
// the value of the expression
assign tc = (cet && (count == length-1));



endmodule

...
reg a, b, c, d;
wire e;
...
always @(b or e)
begin
 a = b & e;
 b = a | b;
 #5 c = b;
 d = #6 c ^ e;
end

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